By continuing to browse, you accept the use of cookies for the purposes of authentication and adding favourites. Find out more
STMicroelectronics vacancy search engine

Design H/W Staff Engineer M/F

General information


  Location: Asia-Pacific, India, Greater Noida

Type of contract: Regular

Job open date: 28/02/2020

Company department: Digital Verification Engineer


 STMicroelectronics is a leading semiconductor company, a world key player thanks to our 43,200 employees including 8,300 working in R&D.

 ST’s products are found everywhere today. And together with our customers, we are enabling smarter driving, homes, factories, and cities, along with the next generation of mobile and Internet of Things devices. Everywhere microelectronics makes a positive contribution to people lives, ST is there.

 In 2018, we were ranked by the Randstad Employer Brand Research Award among the 5 most attractive companies in France, for our values of excellence, our integrity and the respect of our employees.



The Imaging division is a worldwide organization (Europe, US and Asia) that develops and delivers products that use differentiating Imaging technologies. Target applications are numerous and encompass mobile phone, automotive, medical, mass market. Inside the Imaging R&D, the digital verification team is focused on innovative products embedded in the last generation mobile phone or autonomous cars. During the digital design phase (pre silicon), you will be working on the verification plan definition and execution. You will develop, simulate and debug tests using state-of-the-art methods and tools (UVM methodology, tools from Cadence, Synopsys or Mentor). You will interface with the main R&D contributors (architecture / design / FW / DFT / FPGA / analog) and you could interface with our customers.



  •    Education Level Required - B.Tech(Electronics), Years of Work Experience - 5 to 10, Desired Competencies are  - HW/SW Coverification Techns, Digital Strategy Verification.The Other skills required are UVM based verification methodology, System Verilog
    SoC verification
    Gate level simulations
    Well versed with SV-UVM, Verilog, C, scripting
    Functional and code coverage
    Test bench development
    Experience in Low Power and Formal Verification techniques
  •  5 - Master degree
  •  6-10 years



 Learn more about STMicroelectronics on:

And ask you questions:

  • LinkedIn : STMicroelectronics
  •  Facebook : STMicroelectronics

Offer__2019-441_Design H/W Staff Engineer M/F