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STMicroelectronics vacancy search engine

Senior staff Digital Designer FE M/F


Vacancy details

General information

Reference

2020-7123  

Job level

40 - Experienced

Position description

Posting title

Senior staff Digital Designer FE M/F

Regular/Temporary

Regular

Job description

Responsibilities include :

  • Technical Lead/Senior RTL Design Engineer who will be responsible for design and development of all digital IP designed for Automotive SoC.

  • Responsible of CPU subsystems and a set of Digital IPs for all PowerCore/ARM based ADG products.

  • Plan, manage, design and deliver entire digital IP(s) portfolio as per project plan.

  • Responsible for life-cycle of IPs including but not limited to IP definition, development and defect tracking of IPs.
    Responsible along-with Systems team for the IP and product architecture document.

  • To deliver IP(s) to SoC teams, support for synthesis, verification and validation.

  • Lead the design quality procedures and processes in the digital IP team.

  • To benchmark architecture choices and share the results with Systems team and customers.

  • PPA activities with new CPUs/Interconnect in ST’s latest automotive technologies.

  • Person will be responsible for communication with customers, system engineers, project leaders and application.

  • To support, guide, motivate team members.
    Technical review of all IP designs, coverage, area, performance and best coding practices.

Profile

Technical background/Key Skills:

 

  • Interconnect Protocols- AMBA- AXI, AHB, APB, Packetization.
  • NoC topology, Bridges, architecture design and Performance monitor.
  • ARM based Micro-Architecture Development, Processor Core IP Integration.
  • Experienced in RTL Coding (verilog/systemverilog/VHDL), Linting, CDC, Simulation & Debugging.
  • Perform RTL Design and Coding for logic related to Clocking, Reset, Power Management, design partitioning and Interface logic.
  • Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL.
  • Exposure to physical design, Sythesis, STA and verification methods.
  • Creative, self-motivated, and able to work comfortably in a cross-site team environment.
    Balance performance, power, safety, and cost requirements.
  • High performance (low latency, high bandwidth) design techniques.
  • Strong technical and problem solving skills.
  • Knowledge of scripting languages. Perl and Python are pluses.
  • Experience in microcontroller architecture, Cache, protocols like AHB/AMBA,AXI, Memory(Flash,SRAM,DDR) and memory controllers will be preferred

Leadership Skills :


  • Proven track record of leadership role in managing high level complex digital IP(s), driving teams and coordinating, resolving conflicts.

  • Adaptability to different roles aligning with business needs, start-up attitude and able to balance resources, time constraints environment well

  • Good communication and interpersonal skills

Position localisation

Job location

Asia-Pacific, India, Greater Noida

Candidate criteria

Education level required

4 - Bachelor degree

Experience level required

Over 10 years

Languages

English (2- Business fluent)

Requester

Desired start date

10/11/2020