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STMicroelectronics vacancy search engine

ESD Static Protection Design and Customer Support engineer


Vacancy details

General information

Reference

2020-3990  

Job level

40 - Experienced

Position description

Posting title

ESD Static Protection Design and Customer Support engineer

Regular/Temporary

Regular

Job description

Introduction to ESD team: The mission of the ESD team is “Provide end-to-end optimized on-chip ESD & LUP solutions along with verification methodologies and support in all TDP technologies”. To achieve this mission, the team is divided into several operational and transversal competence centers. Our deliverables are customer supports, ESD IP libraries, ESD / LUP characterizations, product debugs, library qualifications or product ESD verification supports. The activities of the team are dispatched in the different competence centers who manage their own tasks in the way realize the requested deliverable in cohesion and team spirit. You will be in the ESD Device and LUP operational and Customer Support transversal competence centers. The ESD team works in a multi-site context in between India and France so the English language is necessary to communicate with the whole team.
You will directly report to ESD Team manager and collaborate closely with ESD Devices and LUP accountable, Program Manager and the Technology Program Manager for sync up as well as on delivery, planning and resource purposes.
This position is an important activity regarding static ESD protection design, DOE design and delivery, ESD IPs Library formatting and delivery, Library Qualification/DOE characterization analysis and granting.
Another aspect of this job is the management of tickets and IPneeds in Helpdesk website tool. It requires to spend time on tracking new tickets and new IPneeds and on dispatching through the different competence centers after providing first level answer as well as maintaining our visual weekly Customer Support page.

The main job functions are:
Provide Design and Layout of ESD static protections.
ESD IPs Library formatting and Delivery on UPT+.
DOE of ESD structures elaboration, conception, design, layout, MIM reservation, finishing and delivery, entering “ewip” request for characterization and qualification.
Involve in DOE characterization analysis step and provide the resulting report.
Involved in Library Qualification analysis and provide the resulting report.
Analysis could lead to deeper study by entering Failure Analysis request and conclude on physical analysis.
Can be involved in other operational activities in the team depends on team loading and own interest.

Day to day activities:
Layout tasks, DRC/LVS checks, Library formatting, deal with UPT+
MIM, ESD ewip, FA request/reservation entering
Delivery of DOE and Library to MIM or UPT+
Interactions with DRM team, FA team, ESD lab  and internal  ESD DEVICES/LUP competence center accountable and PM/TPM for planning and relevant information purposes.
Analyze Qualification report, enter in deeper study if necessary and provide updated report
Analyze Characterization results, enter in deeper study if necessary, highlight unexpected ESD IP behavior and provide characterization report
Helpdesk management by listing new IPneed and Ticket, providing first step answers and dispatc

Profile

Master’s degree or equivalent or higher in electronics / microelectronics
5-6 years of experience in a similar or partially similar environment.
Knowledge on semiconductor physics and Cadence Virtuoso (Analog Design Environment is a plus)
Good communication as natural behavior, customer-oriented mindset, abilities for transversal work and teamwork. Motivated by learning and results.
Accountability, self-organized, rigorous, autonomous (interdependent).  
Language: French and English (2- Business fluent)

Position localisation

Job location

Europe, France, Crolles

Candidate criteria

Education level required

5 - Master degree

Experience level required

2-5 years

Languages

  • French (3- Advanced)
  • English (2- Business fluent)

Requester

Desired start date

20/01/2020