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STMicroelectronics vacancy search engine

Digital UVM Verification Engineer

General information


  Location: Europe, United Kingdom, Edinburgh

Type of contract: Regular

Job open date: 27/09/2020

Company department: Digital Design FE


 STMicroelectronics is a leading semiconductor company, a world key player thanks to our 43,200 employees including 8,300 working in R&D.

 ST’s products are found everywhere today. And together with our customers, we are enabling smarter driving, homes, factories, and cities, along with the next generation of mobile and Internet of Things devices. Everywhere microelectronics makes a positive contribution to people lives, ST is there.

 In 2018, we were ranked by the Randstad Employer Brand Research Award among the 5 most attractive companies in France, for our values of excellence, our integrity and the respect of our employees.



The Role

The position of Digital UVM Verification Engineer requires a motivated individual with strong communication and team-work skills. The candidate should be passionate about verification, with a good knowledge of UVM and enjoy understanding the full system-level view of a product.

The successful candidate will play an important role in the development of new products. This will involve a broad range of verification tasks covering, spec analysis, test plan development, system understanding through technical document review and interaction with other teams (Digital design, Analogue design, Embedded Firmware design, System Architecture and Applications) and implementation of the required verification tests.

Specific responsibilities will include: design and implementation of the project’s UVM environment including SystemVerilog test benches, design and implementation of the required tests for a specific product, script development for automation of non-regression testing, analysis of test results and presentation for review in a test report and contributing to quality reviews with the technical manager.



  •  Key skills & experience

    Relevant degree level qualification
    Solid understanding of digital theory, including static timing analysis (STA) and high-speed/low-power design techniques.
    Proficiency in Verilog HDL/System Verilog, and the C programming language
    Proficiency in SystemVerilog and Universal Verification Methodology (UVM)
    Practical experience in using and creating SystemVerilog test benches
    Good knowledge of scripting languages (PERL, Python…)
    Good knowledge of revision control management (SVN, Git…)
  •  5 - Master degree
  •  Less than 2 years



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