STMicroelectronics vacancy search engine

CPU/DSP Design Manager


Vacancy details

General information

Reference

2023-32229  

Job level

40 - Experienced

Position description

Posting title

CPU/DSP Design Manager

Regular/Temporary

Regular

Job description

STMicroelectronics is a leading semiconductor company specialized in the design of devices for embedded applications in Consumer, Industrial and Automotive fields.

System Research and Application is a Central Division whose mission is to create advanced R&D IPs to bring innovation in the company through the design of new system and product solutions.

One key R&D project is the roadmap of microprocessor and DSP for our internal System-On-Chip design, using both proprietary and RISCV instruction set architectures.

 

The jobholder will manage the design team in charge of the micro-architecture decisions, RTL implementation and FE validation of the processors roadmap and its many derivatives.

He will actively contribute to the design of the processors and act as a technical reference for his strong processor design expertise.

He will report the planning and schedule tasks to the team based on required skills and resources and on project priorities and urgency.

 

In his daily job he will also have strong and fruitful interactions with:

- the architecture team to conceive the better ISA and pipeline macro-architecture and enhancement for the new generation of processors in order to achieve the performance, area and energy efficiency targets for the selected embedded applications, with results better than the competition

- the verification team for the complete validation and testing of the implemented functionalities

- the SW development team (tools and libraries) to clarify limits of the design and ease the performance boost of the new implemented features.
 

Profile

Proven attitude to lead a team and exploit diverse experience level and expertise, people management skills.

Sound knowledge of embedded microprocessor architectures, systems architectures and algorithm profiling.

Experienced in high speed RTL coding, processor and pipeline design, Vector and SIMD unit, HW coprocessor interfaces, multi-scalarity.

Familiar with the whole SoC and IP design flow

Strong analytical and problem solving skills.

Position location

Job location

Europe, Italy, Colleoni

Candidate criteria

Education level required

5 - Master degree

Experience level required

6-10 years

Languages

  • Italian (2- Business fluent)
  • English (2- Business fluent)

Requester

Desired start date

01/05/2023