Intern in IC Digital Design M/F

General information


  Location: Asia-Pacific, Singapore, Ang Mo Kio

Type of contract: Temporary

Job open date: 19/09/2020

Company department: Digital Design FE


 STMicroelectronics is a leading semiconductor company, a world key player thanks to our 43,200 employees including 8,300 working in R&D.

 ST’s products are found everywhere today. And together with our customers, we are enabling smarter driving, homes, factories, and cities, along with the next generation of mobile and Internet of Things devices. Everywhere microelectronics makes a positive contribution to people lives, ST is there.

 In 2018, we were ranked by the Randstad Employer Brand Research Award among the 5 most attractive companies in France, for our values of excellence, our integrity and the respect of our employees.



The Team
The position is an exciting opportunity to be part of a flexible and dynamic team working in the growing markets of image sensor.
The role is within the IC Digital Design team, forming part of the wider design team in Singapore which includes all disciplines required for implementation of full custom image sensors.
In addition to the many challenges of Digital image sensor implementation, the engineer is contributing to tool and flow enhancements
and understanding to all our inter-team colleagues across STs Imaging sites (Grenoble and Edinburgh).
This policy of enhancing skills in each field is greatly encouraged and actively pursued during each project for all team members
The Role
The position of Digital IC Engineer requires the candidate to have basic knowledge in Verilog and/or VHDL
The candidate requires to have interest/motivation in digital verification in IP or/and SOC
The job scope will be mainly focused on digital verification but could also cover implementation and integration of IPs
The candidate must be a team focused and highly motivated individual.
Collaboration with colleagues locally and in the wider design community across the Imaging Division is a key factor for success.



  •  Basic Knowledge and understanding of Verilog/VHDL
    Basic Knowledge with leading edge RTL and gate verification techniques.
    Basic Knowledge of UVM and System Verilog is a plus
    Experience of ASIC synthesis and gate level timing is a plus
    Experience in FPGA synthesis and emulation is a plus
    Knowledge of digital signal processing techniques is a plus
    Excellent interpersonal and teamwork skills, strong communication skills are mandatory.
  •  5 - Master degree
  •  Less than 2 years



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