The candidate will investigate on architectures to obtain LDO with ultra-low quiescent current in no load condition for harvesting application, with fast transient response for line and load variations. It is expected that Sample and Hold techniques will be used. Innovative solutions will be proposed, implemented and validated by simulation and on silicon.

Knowledge of linear and switching regulators architectures.

Knowledge of bandgap architecture, current generators and Sample and Hold techniques.

Knowledge of Cadance Virtuoso IC development environment and spice simulators.

Knowledge of laboratory instrumentation

The Employment search is addressed to candidates of both genders, under Law 10.04.1991 n. 125, as amended by Legislative Decree n. 198/2006 which guarantees gender equality at work