STMicroelectronics vacancy search engine

Front-end Digital Designer M/F


Vacancy details

General information

Reference

2021-10431  

Job level

40 - Experienced

Position description

Posting title

Front-end Digital Designer M/F

Regular/Temporary

Regular

Job description

Introduction.

The position is an exciting opportunity to be part of a flexible and dynamic team in the growing markets of mixed signal chips with signal processing IPs, ARM processor and AMBA bus interface like Wireless Chargers, Bluetooth, PMIC etc. used in Mobile, Tablets, Microcontrollers etc. The role works within the digital design team with the aim to create an efficient Digital Design.

 

 

Job scope.

• Work at SOC level design.

• Creation of Microcontroller based Architecture and SOC RTL code

• Integration of IPs into a SOC 

• Integration of AMBA buses (AHB, APB, AXI) into a SOC 

• Planning UPF flow, Low power Flow, Power aware simulations.

• Planning of Boot simulations and Cosimulations (SW-HW)

• CDC/RDC/LINT

• Verification of architecture using Matlab/Simulink and toolboxes.

• Launching HLS and HLV platforms like Catapult.

• Launching Synthesis, Scan insertion, ATPG.

• STA.

• To manage the development of a SOC from Specs to pg tape, to Maturity, to Production.

• Design of SoC covering microarchitecture definition, propose digital solutions meeting customer’s specification/requirements.

• Leading SoC front-end development activities while closely engaging with cross-functional teams, like digital verification, TEST engineers, PD engineers, Application team, Validation Team, etc

• Work actively with product teams to drive performance, area, and power optimization.

• Risk Management

• To manage the development of an FPGA in parallel

• Schedule preparation at SOC level together with the Program Management and adherence to execution plan.

• Reporting to the Customer and Division management.

• To lead intermediate Design Reviews with the customer (Kickoff, Intermediate Design Reviews, Final Design Reviews) and frequent status calls.

 

 

Profile

• Masters in Electronics' Engineering (a relevant experience with minimum 4 years in a semiconductor or high technology R&D environment would be appreciated)

• Good Knowledge of Microcontrollers (possibly ARM) based Architectures, AMBA bus protocols, Peripherals, Boot, OTP, NVM, RAM, ROM, BIST, JTAG

• Ability to lead a SOC from Specifications to Production, to Product End of life

• Ability to interface with cross-functional teams from New Product Proposal to Product End of life

• Good Knowledge of RISC-V architectures would be appreciated.

• Good Knowledge of most popular technologies (065u, 045u, 032u, 028u, 014u)

• Good Experience in Hardware Design Language (such as VHDL or Verilog).

• Good Experience in CDC, RDC, LINT

• Good Experience in Synthesis, Scan Insertion, ATPG.

◦ Some exposure to Physical Design, including Power analysis, Clock tree Synthesis, Physical Checks

◦ Some exposure to Power Aware, Low power and UPF methodology.

◦ Some knowledge of tools porting from Verilog RTL into C++ would be appreciated.

◦ Some exposure to Scripting languages (PERL, TCL, PYTHON)

• Proficient in Static Timing Analysis

• Good communication and written skills in English.

• Able to work in a multi-cultural team.

• Strong analytical and problem-solving skill.

• Able to keep up with fast moving new design methodology.

 

The Employment search is addressed to candidates of both genders, under Law 10.04.1991 n. 125, as amended by Legislative Decree n. 198/2006 which guarantees gender equality at work
 

 

Position localisation

Job location

Europe, Italy, Catania

Candidate criteria

Education level required

5 - Master degree

Experience level required

6-10 years

Requester

Desired start date

01/05/2021