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STMicroelectronics vacancy search engine

Digital Verification Engineer M/F


Vacancy details

General information

Reference

2019-1965  

Job level

30 - Graduate Entry Level

Position description

Posting title

Digital Verification Engineer M/F

Regular/Temporary

Regular

Job description

- Basic knowledge of UVM/C Digital Verification environment

- Or some experience in UVM/C based methodology, System Verilog & Assertions, shell scripting and ARM SoC verification

- Or strong interest in UVM Digital Verification at IP level or SOC level

 

Profile

 

Exposure to Metric Driven Verification flow with implementation using UVM based methodology. System Verilog & Assertions, Formal verification, C/C++ IP/SoC verification centric
Exposure to working with Architecture, design and software teams to drive the verification activities & ensure micro-architecture and design is fully verified
Strong foundation in SoC architecture and verification of single core/multi-core processors preferably ARM based
Understanding and experience in verification of AMBA Interconnect, DMA controllers, Interrupt handling etc. in ARM based SoC environment
Understanding of compilers and tools for ARM or equivalent processors
Hands on experience in UPF/CPF based Power aware verification (Low power designs)
Hands on experience in Gate level simulations – verification environment bring up and debug
Proficient knowledge of SV, Verilog, VHDL, C/C++, HVL based methodology (UVM) and hands on scripting experience for automation using SHELL/PERL/PYTHON
Understanding of coverage closure goals in SoC Verification
Familiarity with achieving 100% functional coverage, Code Coverage and test plan coverage goals
Hands on experience with Test bench development from scratch, test case coding and execution.
Strong analytical problem solving, and attention to details
Strong skills related to DV Documentation, DV reviews
Strong understanding to derive test plan from design specification.
 

 

Position localisation

Job location

Asia-Pacific, India, Greater Noida

Candidate criteria

Education level required

5 - Master degree

Experience level required

6-10 years

Requester

Desired start date

01/11/2019


Offer__2019-1965_Digital Verification Engineer M/F