In Test Vehicle Engineering (TVE) department, part of TDP organization, you will integrate Semi Custom Design Team.
Our wide-range mission is to specify, develop dedicated chips for state-of-art technologies and libraries qualification, providing support for test and silicon analysis, with strong focus on improvement programs, innovation, and benchmark activities.
As Front-End designer, you will be accountable for several tasks, happening all along the chip development, working closely with physical digital engineers (BE)
- Understand customer requirements and define accordingly block specifications & architecture
- Ensure the testability of the solution with test/analysis/DFT engineers
- Implement designs in RTL language (Verilog or VHDL)
- Validate functionally the system
- Define timing constraints for synthesis and physical implementation
- Launch synthesis, scan insertion aligned our DFT objectives
- Validate the physical database, in terms of functionality and timing constraints and loop with BE engineer to improve/challenge results
- Develop test patterns
- Support test engineers during silicon test sequences
- When required, participate to silicon issue analysis to help progressing on problem solving and so be actor in the quality of the overall design platform solution (process/technology/Ips/libraries offers)
You will work in close collaboration with IPs/libraries providers, technology and design platform owners, tests, and silicon analysis engineers
You will evaluate new design solutions based on state-of-the-art technologies, interacting with design flow teams and EDA vendors (Synopsys, Cadence, Mentor).
Graduated in electronics, you are able to understand digital system architecture and constraints. You have experience in behavioral language (VHDL , Verilog), functional verification, synthesis.
Communication, teamwork spirit, curiosity, dynamism are required for this mission.
Collaborating with teams in several countries (mainly India, Italy...) , English language with business level is required.