Responsibilities:

• Responsible for digital IP design, verification, specification, and documentation
• Create logic designs (RTL) and behavioral models
• Write test benches for block and system verification
• Contribute to ASIC system architectural development

Qualifications/Experience:

• Pursuing Masters / Ph.D.  Electrical Engineering/Computer Science
• Exposure to DSP including digital filters, MATLAB Simulink, and low power design techniques preferred.
• Knowledge of HDL languages such as Verilog / System Verilog / VHDL